Raytheon Technologies Senior Principal Layout Support Engineer in Andover, Massachusetts
The Raytheon Technologies Missiles and Defense (RMD) Microelectronics Engineering & Technology (MET) Department develops, designs, and manufactures compound semiconductor devices, microwave/millimeter-wave integrated circuits, and modules for defense applications. We have an excellent opportunity for a Senior Principal Layout Support Engineer.
As a Senior Principal Layout Support Engineer within the Foundry Services / Design Enablement Group, you will work closely with design engineering teams to digitize and perform physical verification on RF Monolithic Microwave Integrated Circuits (MMICs) using the Cadence Virtuoso tool suite. You will also be responsible for preparing designs for photomask order and delivery into the RMD III-V semiconductor fab.
This is a detail oriented position that requires strong communication skills and the ability to interact within a team environment. As a Sr. Principal Layout Support Engineer, you will also be (1) the primary layout team liaison to the CAD/EDA team responsible for contributing to the modernization and stream-lining of our physical layout and verification flow and (2) the layout librarian responsible for maintaining our standard reference layout libraries.
This position will require a secret clearance.
Providing layout support to MMIC design teams
Chip layout verification using Design Rule Checking (DRC) and Layout Versus Schematic (LVS) tools
Reticle building and photomask ordering
Data checking/peer reviewing chip and reticle layout and related documentation
Specifying, testing, and maintaining layout DRC and LVS verification decks
Specifying and testing SKILL and AEL automation routines
Specifying, developing, testing, and maintaining Cadence and Keysight layout PCells
A minimum of 10 years of professional layout experience
Experience with integrated circuit layout and physical verification
Experience with Cadence and Keysight integrated circuit layout and verification software tools and related scripting languages
Experience developing and maintaining Cadence layout PCells
Proven ability to work within a team environment and follow documented instructions
Strong oral and written communication skills
Experience with Microsoft Office tool suite
Ability to obtain a Security Clearance
Experience developing and maintaining Cadence DRC and LVS verification decks
Experience with layout of microwave/millimeter-wave integrated circuits
Familiarity with III-V semiconductor processing and concepts
Continuous improvement mindset
ASEET or a technical school degree; related experience may be considered in lieu of a degree.
Cadence, layout, HEMT, semiconductor device, microwave, millimeter-wave, digital, analog, Linux, GaN, GaAs, CAD, EDA
This position requires either a U.S. Person or a Non-U.S. Person who is eligible to obtain any required Export Authorization.
Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, age, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.
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