Apple DDR RTL Design Engineer in Boston, Massachusetts
DDR RTL Design Engineer
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Posted:Mar 14, 2023
Role Number: 200469131
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a DDR design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
RTL design using Verilog or SystemVerilog, assertion writing
Design of state machines, data paths, arbitration and clock domain crossing logic
Logic synthesis, timing constraints
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Prior experience in DDR PHY design and mixed-signal environment is a plus
In this role, you will be responsible for the following: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.
Education & Experience
BS degree in technical discipline with minimum 3 years of relevant experience.
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