Intel Lead Test Engineer in Boston, Massachusetts
The DPEA MIO (Memory Technology and Standards group) is looking for an experienced Lead Test Engineer to join our memory pathfinding and engineering team. Come join the inventors driving next generation standards and technologies and work directly with the memory architecture team that's helped shape many generations of memory standards in the industry. This position provides an exciting opportunity to become a member of the Memory and IO Technologies team (MIO) in DPEA (Data Center Platform Engineering) and be at the driving seat to help shape the next generation memory technologies and standards (next generation DDR solutions, next generation LPDDR and beyond).
As a Lead Test Engineer you will work with Intel's MIO team that defines the standards for Intel's most strategic technologies and interfaces. If you have experience in memory testing, Intel architecture and DDR memory subsystem, proven ability to lead cross-functional technical teams to drive resolution of critical problems while working in lab environment and want to work with an exciting team on cutting edge memory technologies, we would like to hear from you.
As a Lead Test engineer you are: Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Good understanding of DRAM architecture, test equipment, operations and programming, high-speed electronics test fixtures, system architecture and system level testing. Capable of making significant contributions to design, development and validation of testability circuits. Work with product architects and engineers to define DFX (design for testability) hooks in the component during the technology development phase to improve test coverage and reduce external test requirements. Comprehends memory component suppliers capability and align them to Intel requirements, with strong emphasis on correlating the test results between the parties to ensure highest quality memory is available to support Intel's products. Evaluation, development and debug of complex test methods.
Familiar with ATE hardware and test industry capabilities. Develop and debug software programs to convert design validation vectors and drive test equipment. Purchase and deploy test equipment/hardware: Hardware with sufficient bandwidth, test channels, load board design to test Components (DRAM, RCD, DB, etc.) and Modules (DIMMs), as required by technology and aligned to Intel product schedule. Generate test plan and test coverage: Understand ATE test limitations and gaps against how system interacts with memory compared to ATE (Example: BIOS trains memory in a non-ideal system channel using proprietary algorithms; Define how much can/must the ATE replicate the system level memory capability and behavior. Define and drive test automation to handle component and DIMM level testing for unattended testing as required by the technology. Assess test infrastructure and resource capabilities, both at Intel and Intel suppliers. Ensure that the new technology specifications can actually be tested to determine pass/fail criteria, if not guaranteed by design. Analyze early customer returns with emphasis on driving test coverage gaps. Create and apply concepts for optimizing component production relative to both quality and cost constraints. Ability to independently plan and schedule daily tasks, generate decision matrix and recommendation on reconciling decisions such as test hardware vs procuring new. The objective and deliverable of the job function may be summarized as providing device, DIMM, and system level test coverage that meets Intel quality requirements, aligned to Intel technology roadmap.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
7 years' experience leading engineering teams (10-15 preferred) 10 years memory industry experience in DRAM design, architecture, and/or testing, preferably in APAC Geo.
Must be willing to travel to Korea to support the team locally
Experience to manage a test organization, identifying and hiring the right talent and skillset.
Experience working with major DRAM memory vendors, validation of DDR, LPDDR, HBM, and/or other memory devices and expert debug capabilities at component and system/platform level Demonstrated industry influence with DRAM suppliers, OEM/ODMs, and/or test equipment manufactures
Experience in Xeon and Client Memory Controller and System Memory validation and deep understanding of HW/SW/BIOS/OS interactions
Experience working in cross-org teams to lead debug of memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, manufacturing, System Hardware and Software
Must be able to outsource testing based on external vendor/supplier capabilities, against Intel's resource limitations and prioritize multiple technologies at multiple geographies based on schedule and skillset level
Hands-on experience in using industry standard JTAG, I2C, and memory testers such as Advantest 93000 and Teradyne memory testers
Experience in developing test cases for Machine Learning, High Performance Computing, Server Clusters
Experience with writing code that improves and/or optimizes BIOS and Test tools performance, test coverage, stress testing and test time reduction
Project management skills to forecast capital expenditure, get stakeholder buy-in, resource allocation, schedule and milestones.
Good organizational and communication skills are a must, given the capital investment and the longer development cycles
Qualified candidate would have experience in at least one or more of these memory technologies:
DDR - all versions LPDDR - all versions
I2C/I3C Fully Buffered DIMM
Experience with integrated products (Example: HBM, Soldered down memory, Memory on Package)
DDR5, LPDDR5 knowledge
Fab experience would be excellent
Proficient in Korean Language
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Inside this Business Group
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $136,750.00-$232,630.00
*Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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