Apple Semi-Custom Physical Design Engineer in Boston, Massachusetts
Semi-Custom Physical Design Engineer
In this role, you will be part of the Analog Mixed Signal (AMS) team collaborating with architecture, Circuits, CAD, timing and logic design teams, with a critical impact on delivering outstanding Semi-Custom Physical Designs. You will be required to do semi-custom high speed and ultra-low power physical designs of state-of-the-art mixed-signal designs.
Preferred at least 5+ years of physical design experience on mixed-signal and/or SOC designs
Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
Deep knowledge or experience with digital signal processing filters design, analog-on-top mixed signal physical and timing interface implementation techniques, and passion to pursue out-of-the-box physical implementation techniques to achieve uncompromised design goals
Meaningful experience in developing and implementing Power-grid and efficient Clock Distribution Networks
Deep Understanding of all aspects of Physical construction, Integration, Design-For-Test (DFT), and Physical Verification
Confirmed Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to communicate with logic design team for timing fixes. Power user of industry standard Synthesis, Physical Design, Timing & Power Analysis tools
Deep Understanding of scripting languages such as Perl/Tcl
Deep Understanding and working knowledge of STA methodology, constraints, and tools
Working knowledge of Physical Design Verification methodology to debug LVS/DRC issues at block level
As a Semi-Custom Physical Design engineer, you will chip in to all phases of physical design of high performance Analog Mixed Signal designs from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to the following: Generate block level static timing constraints. Build block level floorplan including pin placement and power grid. Develop and validate high performance low power clock distribution network. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at block level and to provide guidelines to fix LVS/DRC violations. Participate in establishing CAD and physical design methodologies for accurate by construction designs. Assist in flow development for Analog-On-Top integration.
Education & Experience
Requires 4+ years of industry experience and Masters, or PhD Degree in a technical subject area.
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