VIVA USA Inc Design Verification Engineer in Boxborough, Massachusetts
Req Ref No: LSMADV152 Location: Boxborough, MA Duration: 6.0 months
Integration and functional verification for a block of complex IP's for a combined CPU/GPU development effort Work closely with a team members to understand and verify new design features Debug of Verilog RTL and System Verilog & C/C++ testbench at the IP and/or SOC-level
EXPERIENCE AND EDUCATION:
10 or more years of proven verification experience on large ASIC development Experience with large SoC build, debug, and general DV is required. Knowledgeable in C/C++, OO programming, Verilog, System Verilog, and scripting languages (Perl, etc) Familiar with constrained random verification Excellent debug skills, ability to analyze and isolate design/testbench issues using various techniques including waveforms and log files. Familiar with hardware modeling and/or assertion-based verification methods Excellent written and communication skills Background in GPU/CPU architecture along with significant memory system and /or SoC architecture experience is important.
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.