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Microsoft Corporation Senior Hardware Engineer in Cambridge, Massachusetts

Come join us in blazing the trail for FPGA-based AI acceleration at datacenter scale! By leveraging the huge amounts of fine-grained parallelism delivered by current and future FPGAs, reconfigurable computing can radically accelerate many types of computations. We are applying this technology to challenging applications important to Microsoft and our customers, including Bing and Office. Our work includes developing, optimizing, deploying, and maintaining FPGA accelerators, infrastructure, and tools.

Our current focus is on accelerating deep neural networks (DNNs) via the Brainwave accelerator architecture. We are heavily involved in developing, extending, and deploying Brainwave, and in bringing DNN models to production on FPGAs using Brainwave. Working with Microsoft model developers to deploy their models on Brainwave gives us the unusual opportunity of working across the whole DNN stack, from cutting-edge DNN models, techniques, and frameworks to accelerator architecture.

This cutting-edge development takes place in the context of a live, global-scale distributed system that touches millions of users daily, running on the world’s largest distributed FPGA-accelerated hardware platform.

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Responsibilities

  • Design and specify major IP blocks for cloud-scale machine learning accelerators.

  • Perform design space exploration including architectural studies, workload analysis, and PPA characterization.

  • Incorporate best-of-breed research and industry practices into designs and development processes.

  • Engage with customers, team members, and engineering stakeholders to solicit and incorporate feedback.

  • Deliver detailed documentation of design interfaces, datapaths, and control.

  • Implement and deliver high-quality IP authored in synthesizable RTL that meets design specifications and requirements.

  • Enable bring-up of hardware features in lab and production environments.

  • Develop software and test harnesses to exercise and debug new functionality in simulation and lab hardware.

  • Deploy hardware features and functionality into live datacenters. Troubleshoot and monitor for issues at scale. Support customers.

Qualifications

Required Qualifications:

  • B.S or higher preferably in computer engineering, computer science, or related fields or equivalent work experience

  • 5+ years of experience with RTL development (Verilog / VHDL or equivalent) on FPGAs or ASICs

Preferred Qualifications:

  • M.S. or PhD in EE, ECE, CE, CS or related fields

  • Background in computer architecture and embedded systems

  • 5+ year experience in SoC/embedded systems programming experience in C/C++ 8+ years of experience with Verilog or VHDL and design floor planning, timing closure and IP integration on FPGAs

  • Experience in hardware design verification using SystemVerilog, OVM, UVM or similar infrastructure

  • Familiarity with machine learning and deep learning

  • Strong communication skills and the desire to collaborate in a team of engineers.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form (https://careers.microsoft.com/us/en/accommodationrequest) .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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