Apple SoC Memory Performance Architect in Cambridge, Massachusetts
SoC Memory Performance Architect
Solid knowledge of cache management and memory controller for DRAM technologies. Prior experience on writing a cache and memory simulator using C++ is a big plus.
Excellent C/C++/scripting coding, debug, and testing skills.
Papers published in top computer architecture conferences/journals and filed patents related to computer architecture, demonstrating ability of designing and evaluating different cache and memory performance techniques
Prior work on analyzing the memory access patterns and bandwidth/latency requirements of CPU, GPU, Video, Camera, Machine Learning hardware accelerators or similar areas.
Expertise in cooperative code development using a revision control system such as GIT.
Strong communication and documentation skills.
You will have responsibilities for developing the SoC hardware solutions that drive the architecture of Apple’s future System-on-Chips. Your work will be highly visible and critical to delivering the best performance and power efficiency in Apple’s future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple’s SoC development: - C++ performance modeling of proposed architectural solutions and features. - Writing architectural specification documents in collaboration with engineers across different disciplines. - Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives. - Work with the multi-functional teams to develop architectural solutions. - Improve Apple’s modeling platform by developing APIs, tools, and optimal standard examples that can be used throughout the company. - Carefully analyze and present results to enable data specific architecture/design. - Measure and analyze existing SoC and workloads. - Some international travel is required for this position.
Education & Experience
MS or PhD in CS, EE, or related field.
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