Intel IP Validation Engineer in Hudson, Massachusetts
As a Digital IP Validation Engineer, you will be part of the exciting work being done by the logic validation team within Intel's Scalable CPU Performance Group (SDG). In this role you will develop pre-silicon functional validation tests to verify the logic and system will meet design requirements. You will create test plans for RTL validation, define and run system simulation models, and find and implement corrective measures for failing RTL tests. You will analyze and use results from execution of test cases to modify and enhance the validation process
Bachelor's degree (Master's preferred) in Electrical Engineering or Computer Engineering or Computer Science with 5+ years of experience in Pre-Silicon Logic Verification.
Experience with SystemVerilog, methodologies like OVM/UVM, and with OOP techniques.
Experience with c reation of test plan, coverage closure, test case and regression suite development.
Experience with d ebugging RTL issues, regression failures, and verification environment issues, including class-based verification components.
Preferred (Additional) Qualifications
Understanding of Verification IP architecture for any complex protocol especially mixed signals (with digital/analog blocks) would be an added advantage.
Strong problem-solving debugging skills.
Solid verbal and written communication skills.
Motivated, self-directed and can work effectively both independently and in a team.
Scripting language nice to have (PERL, PYTHON, Shell Scripting)
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
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