Intel IP Verification Engineer in Hudson, Massachusetts
Join our world-class IP development team. In this role you are a pre-silicon verification/validation engineer and member of an IP development team. Our team is chartered with delivering differentiating memory controller IP and subsystems to multiple Intel server SoCs, across the Intel product portfolio.
Responsibilities include but are not limited to:
Defining and implementing verification environments that include use of constrained-random stimulus and functional coverage.
Compiling and executing test plans that guarantee thorough verification of the controller features and functionality.
Writing System Verilog Assertions (SVA), monitors, checkers, scoreboards, stimulus, test sequences, and directed tests.
Analyzing test failures with ability to debug to root cause, then assisting in defining preferred fix.
Participating in improvements to the validation environment that drive down validation escape bug rates.
In addition to the responsibilities listed above, the ideal candidate will also have:
System Verilog UVM validation expertise.
Excellent analytical and problem-solving skills.
Solid verbal and written communication skills.
Capability as an effective team player with a continuous learning mindset.
Willingness to balance multiple tasks in an exciting, fast-paced development environment.
Willing to read and interpret technical specs to understand IP functional behavior.
Understanding of Register Transfer Level (RTL) code written in Verilog and System Verilog (SV).
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have:
Bachelor's degree in Electrical/Computer Engineering or Computer Science.
And experience in IP verification using Verilog or System Verilog and Open Verification Methodology (OVM) or Universal Verification Methodology (UVM).
- Experience in development and verification of memory controllers for DDR or HBM memory technologies.
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
US, Arizona, Phoenix;US, California, Folsom;US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro;US, Texas, Austin
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Annual Salary Range for jobs which could be performed in US, Colorado:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here (https://www.intel.com/content/www/us/en/jobs/benefits.html)
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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