Intel Pre-Silicon Validation Engineer / Lead in Hudson, Massachusetts
Are you passionate about disrupting the industry with your innovation? Working with a diverse group? Influencing the outcome? If so, then Xe Silicon Engineering (XSE) team has an opportunity for you.
This team focus on designing, validating and delivering all silicon that drives our Xe product roadmap. The FC/Emulation team is within XSE and we are charter with SoC validation to Intel's upcoming Xe GPU products. You will be own a part of the SoC validation and manage it at every level subsystem level, SoC and Product(multi-die). The actual domain assignment would be based on your expertise and interest.
In this position you will help us with the following responsibilities:
Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
Develop debugging tools, methodology and software to participate in the debug of failures on emulation/silicon platforms, find the root causes and report bugs to respective teams.
Communicate effectively, coordinate and work with IP Design and SoC integration teams.
Mentor junior members and contractors.
For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information (https://www.intel.com/content/www/us/en/jobs/hiring.html) .
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.
Minimum Qualifications :
- Bachelor's degree in Electrical/Electronics/Computer Engineering or related fields with 5 + years of relevant industry experience.
- Master's in the same fields with 3+ years of relevant industry experience.
Your experience should be in the following:
IP/SoC Verification/Validation (Verification environment, Test writing, Debugging etc ).
SoC Architecture and serial bus protocols(I3C/SPI/USB/PCIe).
Programming with SystemVerilog and Open Verification Methodology (OVM)/Universal Verification Methodology (UVM).
C/C++ programming skills and experienced in Object-Oriented Programming (OOP) concepts.
Experience with one or more of the following: Hardware Security, Telemetry, Error Reporting.
Experience taking into consideration design modifications that may impact performance, power or cost optimization.
Experience performing Formal verification and assertions using tools like Jasper.
Inside this Business Group
The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center. Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.
US, Arizona, Phoenix;US, California, Santa Clara;US, Massachusetts, Hudson;US, Oregon, Hillsboro
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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