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Intel SOC Design Engineer - IP Structural Design in Hudson, Massachusetts

Job Description

Would you like to work on a high performance CPU design? Would you like to implement designs in a state of the art process technology?

We are a trusted, innovative IP design team delivering High Performance DDR PHY design for Intel's Data Center products. We are designing innovative IP for the next generation of CPU's that will fuel Intel's growth in Datacenter and the virtuous cycle. We are looking for an outstanding design engineer to join our engineering team. You will collaborate with architects, logic designers, and analog engineers in evaluating implementation details of complex design features. You will perform all aspects of the SoC design flow from high-level design through synthesis, place and route, timing analysis and power reduction. You will be responsible for creating a design database that has completed sign-off flows and is ready for manufacturing.

Responsibilities of the role include, although not limited to:

  • IP Family and/or block-level floor planning

  • Power supply and power grid planning and analysis

  • Logic synthesis of design blocks- Formal Equivalence Verification (FEV)

  • Clocking network planning and analysis

  • Auto Place-and-Route (APR) using Synopsys ICC tools

  • Timing verification using Synopsys PrimeTime

  • Physical verification

  • Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC), and Design for Manufacturability checks (DFM)

  • Reliability Verification

  • Debug and resolution of integration issues at parent level

  • Completion of design reviews and design signoff flows

  • Assist in the preparation of the full-chip layout design database for introduction to manufacturing


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

Candidate will have a Bachelor's in Electrical or Computer Engineering, or related field and 1+ years of experience -OR- or Master's Degree in Electrical or Computer Engineering with:

  • CMOS transistor level circuit fundamentals

  • VLSI hardware design

  • Scripting programming (Perl, Python, or TCL)

Note: This position is not eligible for employment-based visa/immigration sponsorship for those with a Bachelor’s degree and less than 3 years of experience. Intel sponsors individuals for employment-based visas for positions where we experience a shortage of US Workers. These skills shortage roles are typically STEM contributing positions requiring a Master's or PhD degree, or a Bachelor’s degree with three years’ related job experience

Preferred Qualifications:

Experience with:

  • Sub-micron CMOS technologies

  • Designing high-speed, low-power digital circuits, floor planning, timing convergence and layout verification

  • Logic synthesis and automated place and route tools

  • Computer architecture and logic design fundamentals

  • Hardware description languages such as Verilog or System Verilog

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.