Intel Xeon SoC Physical Design Intern in Hudson, Massachusetts
In this internship, you will be working alongside a World-class SOC design team within the Xeon Performance Group (XPG) delivering on next-generation Xeon products/IPs for Server markets.
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
Your responsibilities will include but not be limited to:
Block-level floor planning
Logic synthesis of design blocks
Formal Equivalence Verification FEV
Auto Place-and-Route APR using Synopsys or Cadence tools
Timing verification using Synopsys PrimeTime as well as Intel tools
Physical verification Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
Assist in the preparation of the layout design database for introduction to manufacturing
In addition to the qualifications listed below, the ideal candidate will also have the following:
Excellent communication skills
Strong analytical skills
Problem solving skills
Willingess to work independently and at various levels of abstraction
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
The candidate must be pursuing a Master's Degree or PhD in Electrical Engineering, Computer Engineering, or related field.
Willing to commit 6 months to an on site or virtual co-op.
3+ months of experience/coursework with:
CMOS transistor level circuit fundamentals
VLSI hardware design and programming
3+ months experience in:
RTL/Logic design Verilog, VCS, etc.
Electronic Design Automation tools, flows and methodology
ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog
Layout cleanup expertise DRCs, density, ipc, etc.
TCL, Perl and/or C++ programming
Inside this Business Group
Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.
US, Oregon, Hillsboro;US, Texas, Houston;Virtual US and Canada
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Annual Salary Range for jobs which could be performed in US, Colorado:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here (https://www.intel.com/content/www/us/en/jobs/benefits.html)
Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here (https://jobs.intel.com/page/show/candidate-help-desk)
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