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Teradyne ASIC Digital Design Engineer in North Reading, Massachusetts

Organization & Role

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions helps manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!.

Responsibilities

Teradyne’s Silicon Technology Engineering (STE), ASIC Integration Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry for our customers to ship production chips/products.

You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup.

In this role you will be responsible for:

  • Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect

  • Integration of industry standard and Teradyne custom IPs

  • Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success

  • Providing timing constraints and STA support to the Physical Design team through timing closure

  • Providing post silicon lab bringup and debug support

Basic Qualifications & Skills

  • Logic design experience writing RTL in Verilog

  • Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT

  • Experience with logic synthesis and timing constraints

  • Experience with clock domain crossings (CDC) and static timing analysis (STA)

  • Experience with high-speed memory interfaces, Serdes and PCIe preferred

  • Experience with automation through scripting such as Perl, Python, Tcl & Make

  • This position requires employees to be fully vaccinated or subject to weekly testing for onsite access.

Education

  • BSEE/MSEE

#LI-NINJA

Current openings may involve access to export controlled technology and may be subject to export licensing requirements prior to employment. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form. In addition, you may also contact the HR Service Center at 978-370-3041 or contact them at HR.Service.Center@teradyne.com for additional assistance. LitePoint, a Teradyne Company is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor.

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